Role
Solo project
A three-board FPGA system designed to measure a complete tick-to-trade path over physical wires. The project will combine Arm/FPGA co-design, a pure-RTL trading engine, and an independent latency auditor.
System architecture drafted. Protocol definition, RTL implementation, verification, hardware bring-up, and measured results are still to come.
Arm HPS streams historical ticks over AXI. FPGA logic frames and transmits them over GPIO.
Parses frames, maintains an L2 order book in BRAM, and emits a trade signal.
Passively timestamps market-data and trade signals to measure end-to-end latency.
Build a physically measurable FPGA trading pipeline that demonstrates the skills used in low-latency financial systems: deterministic RTL, clock-domain crossing, on-chip data structures, AXI integration, verification, and evidence-led latency analysis.
The system separates stimulus, decision, and measurement across three boards. A DE0-Nano-SoC publishes market data, a Basys 3 processes it without a CPU, and a second DE0-Nano-SoC independently measures the wire-level response. Keeping the auditor separate avoids relying on self-reported timing from the trading engine.
The target is not just low latency; it is latency that can be measured, explained, and reproduced.